This invention relates to digital image processing, in general, and more particularly, to an improved method and apparatus for interfacing a digital image processor with an analog video input and output.
In various types of image processing systems such as the fluoroscopic system described in application Ser. No. 568,013, filed on even data herewith, there is a need to convert data from one of more types of analog video signals to digital format and, after processing, convert back to analog format. Particular problems arise when it is desired to operate on square pixels (i.e., picture elements which make up an image with a square aspect ratio) when receiving inputs from a device having a rectangular aspect ratio format and also in operating with elements of the image processing system which cannot operate at the same speed as the incoming input data rate.
As disclosed in the above application, the interlaced configuration in a standard television camera has an aspect ratio of 4:3, i.e., the frame width is four (4) units wide and the frame height is three (3) units high. A sequential scan camera on the other hand normally has a 1:1 aspect ratio, i.e., it displays a square picture. It is desirable to process video signals that represent square pictures and square pixels of the image (i.e., square aspect ratio signals). Typically, cameras will utilize an image intensifier tube, which is generally circular and does not have an aspect ratio of 4:3, for image enhancement. In such case, when a conventional television camera with an interlaced scan and 4:3 aspect ratio views an image via an image intensifier tube, the image will be contained within a square in the middle of the television camera screen or raster.
If one considers a line of pixels on a television raster with a 4:3 aspect ratio and 512 lines of vertical resolution, the number of square pixels generated across each line will be approximately 4/3 times 512 or 682 pixels. The image information, however, will be contained only within the 512 pixels in each line in the center of the screen on which the circular image intensifier image is located. Thus, in converting the analog video signal of the image when it is obtained from a conventional interlaced camera, there should be a delay at the beginning and end of each horizontal scan. For example, data conversion should start only after pixel number 85 is reached and continue for 511 additional pixels to pixel number 597. This yields digital data representing a 512 by 512 array of square pixels. Similar delays have to be introduced when converting the data back into analog format, i.e., only in the area between and including pixel 86 and pixel 597 should video information be reconverted.
Secondly, there is a certain amount of time alloted for scanning across a line and converting data for 512 pixels at a basic horizontal frequency for an image processing system of 10 MHz, for example, plus a time for retrace. When scanning with a camera having a 4:3 aspect ratio, one and one-third as many pixels must be scanned in this time. Thus, it is necessary to accelerate the rate of data conversion by four-thirds in order to scan 512 pixels in the center portion of the screen within the alloted time. For this reason, at the input, and again at the output, a clock accelerator is necessary to carry out the required acceleration for the 4:3 aspect ratio of the input and the display output.
Finally, it is difficult with presently available hardware to carry out frame processing in the frame processors of an image processing system at 10 MHz. Since there is a considerable amount of time utilized in retrace in a scanning corresponding to a data conversion at 10 MHz, it becomes useful to utilize this time for computation within the frame processors. Consequently, information can be operated on continuously in the frame processors at a lower frequency.